ワダ ヤスタカ   WADA Yasutaka
  和田 康孝
   所属   情報学部 情報学科
   職種   准教授
言語種別 英語
発行・発表の年月 2019/06
形態種別 学術雑誌
査読 査読あり
標題 Deep Learning Acceleration with a Look-Up-Table Based Memory Logic Conjugated System
執筆形態 共著
掲載誌名 Transactions of The Japan Institute of Electronics Packaging
掲載区分国内
巻・号・頁 12,pp.E18-008-1-E18-008-7
総ページ数 7
著者・共著者 Daisuke Ogawa, Yoichi Sato, Yasutaka Wada, and Kanji Otsuka
概要 This paper is the progressive study of previous papers presented at the IMPACT 2015 and ICEP 2018, and evaluates effectiveness and applicability of MLCS (Memory Logic Conjugated System) with a simple deep learning processing. NVIDIA, Google, Fujitsu Intel-Altera, Intel-Nervana and Renesas recently announced that 8 bits processing can keep efficient and flexible AI computation, peculiarly in deep learning. This paper discusses on the actual MLCS circuit implemented on a commercial FPGA for deep learning, and evaluate the circuit with perceptron method for deep learning. In the MLCS architecture, deep learning computations can be done as memory operations. Our architecture can achieve its high I/O bandwidth and low-power consumption with dynamic reconfiguration functionality, high-speed connection among logics and memory cells, and low implementation cost.
DOI 10.5104/jiepeng.12.E18-008-1
ISBN 1883-3365
ISSN 1884-8028