ワダ　ヤスタカ   WADA Yasutaka   和田　康孝    所属   情報学部 情報学科    データサイエンス学環    職種   教授
言語種別	英語
発行・発表の年月	2007/06
形態種別	その他の著書・論文
査読	査読あり
標題	Heterogeneous Multiprocessor on a Chip Which Enables 54x AAC-LC Stereo Encoding
執筆形態	共著
掲載誌名	Proc. of The 2007 IEEE Symposium on VLSI Circuits
出版社・発行元	IEEE
巻・号・頁	pp.18-19
著者・共著者	Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Hiroshi Tanaka, Tomoyuki Kodama, Hiroaki Shikano, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, and Hironori Kasahara
概要	A heterogeneous multiprocessor on a chip has been designed and implemented. It consists of 2 CPUs and 2 DRPs (Dynamic Reconfigurable Processors). The design of DRP was intended to achieve high-performance in a small area to be integrated on a SoC for embedded systems. Memory architecture of CPUs and DRPs were unified to improve programming and compiling efficiency. 54times AAC-LC stereo encoding has been enabled with 2 DRPs at 300 MHz and 2 CPUs at 600 MHz.
DOI	10.1109/VLSIC.2007.4342719
ISBN	978-4-900784-05-5