ワダ　ヤスタカ   WADA Yasutaka   和田　康孝    所属   情報学部 情報学科    データサイエンス学環    職種   教授
言語種別	英語
発行・発表の年月	2008/04
形態種別	学術雑誌
査読	査読あり
標題	Heterogeneous Multi-core Architecture that Enables 54x AAC-LC Stereo Encoding
執筆形態	共著
掲載誌名	IEEE Journal of Solid-State Circuits
巻・号・頁	43(4),pp.902-910
著者・共著者	Hiroaki Shikano, Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
概要	This paper describes a heterogeneous multi-core processor (HMCP) architecture that integrates general-purpose processors (CPUs) and accelerators (ACCs) to achieve exceptional performance as well as low-power consumption for the SoCs of embedded systems. The memory architectures of CPUs and ACCs were unified to improve programming and compiling efficiency. Advanced audio codec-low complexity (AAC-LC) stereo audio encoding was parallelized on a heterogeneous multi-core having homogeneous processor cores and dynamically reconfigurable processor (DRP) ACC cores in a preliminary evaluation of the HMCP architecture. The performance evaluation revealed that 54times AAC encoding was achieved on the chip with two CPUs at 600 MHz and two DRPs at 300 MHz, which achieved encoding of an entire CD within 1- 2 min.
DOI	10.1109/JSSC.2008.917531
ISSN	0018-9200