ワダ　ヤスタカ   WADA Yasutaka   和田　康孝    所属   情報学部 情報学科    データサイエンス学環    職種   教授
言語種別	英語
発行・発表の年月	2015/06
形態種別	学術雑誌
査読	査読あり
標題	Towards FHE in Embedded Systems: A Preliminary Co-Design Space Exploration of a HW/SW Very Large Multiplier
執筆形態	共著
掲載誌名	IEEE Embedded Systems Letters
著者・共著者	Ghada Abozaid, Arnaud Tisserand, Ahmed El-Mahdy, and Yasutaka Wada
概要	The integration of fully homomorphic encryption (FHE) into embedded systems is limited due to its huge computational requirements. FHE requires multiplications of operands up to millions of bits. Current implementations use high-end and parallel processors, leading to high-power consumption. We propose a hardware-software system to benefit from the best of hardware (performance/low-power) and software (flexibility) capabilities. In this letter, we present our first codesign results for hardware dedicated multiplication units, which is used as atomic operations by the software layer. We report FPGA implementation results for those units and software performance estimations of their use in multiplications up to 16 millions-bit operands. In range of 10 W power consumption, our analysis show that good FHE performance is affordable.
DOI	10.1109/LES.2015.2436372
ISSN	1943-0663