ワダ　ヤスタカ   WADA Yasutaka   和田　康孝    所属   情報学部 情報学科    データサイエンス学環    職種   教授
言語種別	英語
発行・発表の年月	2008/03
形態種別	その他の著書・論文
査読	査読あり
標題	Software-cooperative power-efficient heterogeneous multi-core for media processing
執筆形態	共著
掲載誌名	Proc. of 13th Asia and South Pacific Design Automation Conference (ASP-DAC 2008)
出版社・発行元	IEEE
巻・号・頁	pp.736-741
著者・共著者	Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara
概要	A heterogeneous multi-core processor (HMCP) architecture, which integrates general purpose processors (CPU) and accelerators (ACC) to achieve high-performance as well as low-power consumption with the support of a parallelizing compiler, was developed. The evaluation was performed using an MP3 audio encoder on a simulator that accurately models the HMCP. It showed that 16-frame encoding on the HMCP with four CPUs and four ACCs yielded 24.5-fold speed-up of performance against sequential execution on one CPU. Furthermore, power saving by the compiler reduced energy consumption of the encoding to 0.17 J, namely, by 28.4%.
DOI	10.1109/ASPDAC.2008.4484049
ISBN	978-1-4244-1921-0